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order this document by mc68hc11ka4ts/d ?motorola inc., 1996 this document contains information on a new product. speci?ations and information herein are subject to change without notice. motorola semiconductor technical data m68hc11 ka series technical summary 8-bit microcontroller 1 introduction the mc68hc11ka4 family of microcontrollers are enhanced derivatives of the mc68hc11f1 and, as shown in the block diagram, include many additional features. the family includes the mc68hc11ka0, mc68hc11ka1, mc68hc11ka3, mc68hc11ka4, mc68hc711ka4, mc68hc11ka2, and the mc68hc711ka2. these mcus, with a non-multiplexed expanded bus, are characterized by high speed and low power consumption. the fully static design allows operation at frequencies from 4 mhz to dc. this technical summary contains information concerning standard, custom-rom, and extended-volt- age devices. standard devices are those with disabled rom (mc68hc11ka1), disabled eeprom (mc68hc11ka0), and eprom replacing rom (mc68hc711ka4). the mc68hc11ka2 and mc68hc711ka2 contain 32 kbytes of rom/eprom instead of 24 kbytes. custom-rom devices have a rom array that is programmed at the factory to customer specifications. extended-voltage devices are guaranteed to operate over a much greater voltage range (3.0 vdc to 5.5 vdc) at lower frequencies than the standard devices. refer to the ordering information on the following pages. in this summary, rom/eprom refers to rom for rom-based devices and refers to eprom for eprom-based devices. 1.1 features ?m68hc11 central processing unit (cpu) ?power saving stop and wait modes ?768 bytes ram in mc68hc11ka4, 1024 bytes ram in mc68hc11ka2 (saved during standby) ?640 bytes electrically erasable programmable rom (eeprom) ?24 kbytes rom/eprom, 32 kbytes rom/eprom in mc68hc11ka2 ?prog mode allows use of standard eprom programmer (27256 footprint) ?non-multiplexed address and data buses ?enhanced 16-bit timer with four-stage programmable prescaler ?three input capture (ic) channels ?four output compare (oc) channels ?one additional channel, selectable as fourth ic or fifth oc ?8-bit pulse accumulator ?four 8-bit or two 16-bit pulse-width modulation (pwm) timer channels ?real-time interrupt circuit ?computer operating properly (cop) watchdog ?enhanced asynchronous nonreturn to zero (nrz) serial communications interface (sci) ?enhanced synchronous serial peripheral interface (spi) ?eight-channel 8-bit analog-to-digital (a/d) converter (four channels on 64-pin version) ?seven bidirectional input/output (i/o) ports (43 pins) ?one fixed input-only port (8 pins, 4 pins on 64-pin version) ?available in 68-pin plastic leaded chip carrier (custom rom/otprom), 68-pin windowed ce- ramic leaded chip carrier (eprom), or 64-pin quad flat pack (custom rom/otprom)
motorola mc68hc11ka4 2 mc68hc11ka4ts/d table 1 standard device ordering information package temperature config description frequency mc order number 68-pin plastic leaded chip carrier ?0 to + 85 c $df buffalo rom 4 mhz mc68hc11ka4bcfn4 ?0 to + 85 c $dd no rom 2 mhz mc68hc11ka1cfn2 3 mhz mc68hc11ka1cfn3 4 mhz mc68hc11ka1cfn4 ?0 to + 105 c $dd no rom 2 mhz mc68hc11ka1vfn2 3 mhz mc68hc11ka1vfn3 4 mhz mc68hc11ka1vfn4 ?0 to + 125 c $dd no rom 2 mhz mc68hc11ka1mfn2 3 mhz mc68hc11ka1mfn3 4 mhz mc68hc11ka1mfn4 ?0 to + 85 c $dc no rom, no eeprom 2 mhz mc68hc11ka0cfn2 3 mhz mc68hc11ka0cfn3 4 mhz mc68hc11ka0cfn4 ?0 to + 105 c $dc no rom, no eeprom 2 mhz mc68hc11ka0vfn2 3 mhz mc68hc11ka0vfn3 4 mhz mc68hc11ka0vfn4 ?0 to + 125 c $dc no rom, no eeprom 2 mhz mc68hc11ka0mfn2 3 mhz mc68hc11ka0mfn3 4 mhz mc68hc11ka0mfn4 ?0 to + 85 c $df 24 kbytes otprom 2 mhz mc68hc711ka4cfn2 3 mhz mc68hc711ka4cfn3 4 mhz mc68hc711ka4cfn4 ?0 to + 105 c $df 24 kbytes otprom 2 mhz mc68hc711ka4vfn2 3 mhz mc68hc711ka4vfn3 4 mhz mc68hc711ka4vfn4 ?0 to + 125 c $df 24 kbytes otprom 2 mhz mc68hc711ka4mfn2 3 mhz mc68hc711ka4mfn3 4 mhz mc68hc711ka4mfn4 ?0 to + 85 c $df 32 kbytes otprom 2 mhz mc68hc711ka2cfn2 3 mhz mc68hc711ka2cfn3 4 mhz mc68hc711ka2cfn4 ?0 to + 105 c $df 32 kbytes otprom 2 mhz mc68hc711ka2vfn2 3 mhz mc68hc711ka2vfn3 4 mhz mc68hc711ka2vfn4 ?0 to + 125 c $df 32 kbytes otprom 2 mhz mc68hc711ka2mfn2 3 mhz mc68hc711ka2mfn3 4 mhz mc68hc711ka2mfn4
mc68hc11ka4 motorola mc68hc11ka4ts/d 3 64-pin quad flat pack ?0 to + 85 c $df buffalo rom 4 mhz mc68hc11ka4bcfu4 ?0 to + 85 c $df 24 kbytes otprom 2 mhz mc68hc711ka4cfu2 3 mhz mc68hc711ka4cfu3 4 mhz mc68hc711ka4cfu4 ?0 to + 105 c $df 24 kbytes otprom 2 mhz mc68hc711ka4vfu2 3 mhz mc68hc711ka4vfu3 4 mhz mc68hc711ka4vfu4 ?0 to + 125 c $df 24 kbytes otprom 2 mhz mc68hc711ka4mfu2 3 mhz mc68hc711ka4mfu3 4 mhz mc68hc711ka4mfu4 ?0 to + 85 c $df 32 kbytes otprom 2 mhz mc68hc711ka2cfu2 3 mhz mc68hc711ka2cfu3 4 mhz mc68hc711ka2cfu4 ?0 to + 105 c $df 32 kbytes otprom 2 mhz mc68hc711ka2vfu2 3 mhz mc68hc711ka2vfu3 4 mhz mc68hc711ka2vfu4 ?0 to + 125 c $df 32 kbytes otprom 2 mhz mc68hc711ka2mfu2 3 mhz mc68hc711ka2mfu3 4 mhz mc68hc711ka2mfu4 ?0 to + 85 c $dd no rom 2 mhz mc68hc11ka1cfu2 3 mhz mc68hc11ka1cfu3 4 mhz mc68hc11ka1cfu4 ?0 to + 105 c $dd no rom 2 mhz mc68hc11ka1vfu2 3 mhz mc68hc11ka1vfu3 4 mhz mc68hc11ka1vfu4 ?0 to + 85 c $dc no rom, no eeprom 2 mhz mc68hc11ka0cfu2 3 mhz mc68hc11ka0cfu3 4 mhz mc68hc11ka0cfu4 ?0 to + 105 c $dc no rom, no eeprom 2 mhz mc68hc11ka0vfu2 3 mhz mc68hc11ka0vfu3 4 mhz mc68hc11ka0vfu4 table 1 standard device ordering information (continued) package temperature config description frequency mc order number
motorola mc68hc11ka4 4 mc68hc11ka4ts/d 68-pin cerquad ?0 to + 85 c $df 24 kbytes eprom 2 mhz mc68hc711ka4cfs2 3 mhz mc68hc711ka4cfs3 4 mhz mc68hc711ka4cfs4 ?0 to + 105 c $df 24 kbytes eprom 2 mhz mc68hc711ka4vfs2 3 mhz mc68hc711ka4vfs3 4 mhz mc68hc711ka4vfs4 ?0 to + 125 c $df 24 kbytes eprom 2 mhz mc68hc711ka4mfs2 3 mhz mc68hc711ka4mfs3 4 mhz mc68hc711ka4mfs4 ?0 to + 85 c $df 32 kbytes eprom 2 mhz mc68hc711ka2cfs2 3 mhz mc68hc711ka2cfs3 4 mhz mc68hc711ka2cfs4 ?0 to + 105 c $df 32 kbytes eprom 2 mhz MC68HC711KA2VFS2 3 mhz mc68hc711ka2vfs3 4 mhz mc68hc711ka2vfs4 ?0 to + 125 c $df 32 kbytes eprom 2 mhz mc68hc711ka2mfs2 3 mhz mc68hc711ka2mfs3 4 mhz mc68hc711ka2mfs4 table 1 standard device ordering information (continued) package temperature config description frequency mc order number
mc68hc11ka4 motorola mc68hc11ka4ts/d 5 table 2 custom rom device ordering information package temperature description frequency mc order number 68-pin plastic leaded chip carrier ?0 to + 85 c 24 kbytes custom rom 2 mhz mc68hc11ka4cfn2 3 mhz mc68hc11ka4cfn3 4 mhz mc68hc11ka4cfn4 ?0 to + 105 c 24 kbytes custom rom 2 mhz mc68hc11ka4vfn2 3 mhz mc68hc11ka4vfn3 4 mhz mc68hc11ka4vfn4 ?0 to + 125 c 24 kbytes custom rom 2 mhz mc68hc11ka4mfn2 3 mhz mc68hc11ka4mfn3 4 mhz mc68hc11ka4mfn4 ?0 to + 85 c 32 kbytes custom rom 2 mhz mc68hc11ka2cfn2 3 mhz mc68hc11ka2cfn3 4 mhz mc68hc11ka2cfn4 ?0 to + 105 c 32 kbytes custom rom 2 mhz mc68hc11ka2vfn2 3 mhz mc68hc11ka2vfn3 4 mhz mc68hc11ka2vfn4 ?0 to + 125 c 32 kbytes custom rom 2 mhz mc68hc11ka2mfn2 3 mhz mc68hc11ka2mfn3 4 mhz mc68hc11ka2mfn4 ?0 to + 85 c 24 kbytes custom rom, 2 mhz mc68hc11ka3cfn2 no eeprom 3 mhz mc68hc11ka3cfn3 4 mhz mc68hc11ka3cfn4 ?0 to + 105 c 24 kbytes custom rom, 2 mhz mc68hc11ka3vfn2 no eeprom 3 mhz mc68hc11ka3vfn3 4 mhz mc68hc11ka3vfn4 ?0 to + 125 c 24 kbytes custom rom, 2 mhz mc68hc11ka3mfn2 no eeprom 3 mhz mc68hc11ka3mfn3 4 mhz mc68hc11ka3mfn4
motorola mc68hc11ka4 6 mc68hc11ka4ts/d 64-pin quad flat pack ?0 to + 85 c 24 kbytes custom rom 2 mhz mc68hc11ka4cfu2 3 mhz mc68hc11ka4cfu3 4 mhz mc68hc11ka4cfu4 ?0 to + 105 c 24 kbytes custom rom 2 mhz mc68hc11ka4vfu2 3 mhz mc68hc11ka4vfu3 4 mhz mc68hc11ka4vfu4 ?0 to + 85 c 32 kbytes custom rom 2 mhz mc68hc11ka2cfu2 3 mhz mc68hc11ka2cfu3 4 mhz mc68hc11ka2cfu4 ?0 to + 105 c 32 kbytes custom rom 2 mhz mc68hc11ka2vfu2 3 mhz mc68hc11ka2vfu3 4 mhz mc68hc11ka2vfu4 ?0 to + 85 c 24 kbytes custom rom, 2 mhz mc68hc11ka3cfu2 no eeprom 3 mhz mc68hc11ka3cfu3 4 mhz mc68hc11ka3cfu4 ?0 to + 105 c 24 kbytes custom rom, 2 mhz mc68hc11ka3vfu2 no eeprom 3 mhz mc68hc11ka3vfu3 4 mhz mc68hc11ka3vfu4 table 3 extended voltage (3.0 vdc to 5.5 vdc) device ordering information package temperature description frequency mc order number 68-pin plastic leaded chip carrier ?0 to + 70 c 24 kbytes custom rom 1 mhz mc68l11ka4fn1 3 mhz mc68l11ka4fn3 32 kbytes custom rom 1 mhz mc68l11ka2fn1 3 mhz mc68l11ka2fn3 no rom 1 mhz mc68l11ka1fn1 3 mhz mc68l11ka1fn3 no rom, no eeprom 1 mhz mc68l11ka0fn1 3 mhz mc68l11ka0fn3 24 kbytes custom rom, 1 mhz mc68l11ka3fn1 no eeprom 3 mhz mc68l11ka3fn3 64-pin quad flat pack ?0 to + 70 c 24 kbytes custom rom 1 mhz mc68l11ka4fu1 3 mhz mc68l11ka4fu3 32 kbytes custom rom 1 mhz mc68l11ka2fu1 3 mhz mc68l11ka2fu3 no rom 1 mhz mc68l11ka1fu1 3 mhz mc68l11ka1fu3 no rom, no eeprom 1 mhz mc68l11ka0fu1 3 mhz mc68l11ka0fu3 24 kbytes custom rom, 1 mhz mc68l11ka3fu1 no eeprom 3 mhz mc68l11ka3fu3 table 2 custom rom device ordering information (continued) package temperature description frequency mc order number
mc68hc11ka4 motorola mc68hc11ka4ts/d 7 figure 1 pin assignments for 68-pin plastic leaded chip carrier/cerquad pa6/oc2/oc1 v dd int pa7/pai/oc1 pa1/ic2 pa4/oc4/oc1 pa3/oc5/ic4/oc1 v dd ext pa5/oc3/oc1 pa2/ic1 pd4/sck pd3/mosi pd2/miso pd1/txd pd0/rxd v ss ext pd5/ss 23 24 10 11 12 13 14 15 16 17 18 45 59 58 57 56 55 54 53 52 51 50 19 20 21 22 49 48 47 46 25 60 irq av dd pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 ph1/pw2 ph0/pw1 ph2/pw3 ph3/pw4 xirq /v ppe * pg7/r/w pc1/data1 pc4/data4 pc3/data3 pc2/data2 pc0/data0 pf0/addr0 moda/lir modb/v stby reset xtal extal xout e pc7/data7 pc6/data6 pc5/data5 6 5 4 3 2 67 68 65 64 63 62 8 7 66 9 34 35 36 37 38 39 27 28 29 30 31 32 33 40 41 42 pe6/an6 pe5/an5 pe3/an3 pe4/an4 pf7/addr7 v ss int av ss v rh pf6/addr6 pf5/addr5 pf4/addr4 pf3/addr3 61 44 pf1/addr1 pe7/an7 26 pf2/addr2 43 1 pa0/ic3 * v ppe applies to mc68hc711ka4 and mc68hc711ka2 only. pe2/an2 pe1/an1 pe0/an0 v rl mc68hc(7)11ka4 mc68hc(7)11ka2
motorola mc68hc11ka4 8 mc68hc11ka4ts/d figure 2 pin assignments for 64-pin quad flat pack 14 15 1 2 3 4 5 6 7 8 9 33 47 46 45 44 43 42 41 40 39 38 10 11 12 13 37 36 35 34 16 48 pa1/ic2 pa0/ic3 v dd v dd v ss pd5/ss pd4/sck pd3/mosi pd2/miso pd1/txd pa6/oc2/oc1 pa7/pai/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 pa2/ic1 pe2/an2 v rl pe0/an0 pe1/an1 pe3/an3 v ss pf1/addr1 pf2/addr2 pf3/addr3 pf4/addr4 pf5/addr5 pf6/addr6 pf7/addr7 v ss av ss v rh 61 60 59 58 57 54 55 52 51 50 49 63 62 53 64 extal pc7/data7 e pd0/rxd reset modb/v stby xtal moda/lir pc3/data3 pc2/data2 pc1/data1 pc0/data0 pf0/addr0 pc4/data4 24 25 26 27 28 29 17 18 19 20 21 22 23 30 31 32 pb7/addr15 pb6/addr14 pb4/addr12 pb5/addr13 ph3/pw4 ph2/pw3 ph1/pw2 ph0/pw1 xirq /v ppe * pg7/r/w irq av dd 56 mc68hc(7)11ka4 mc68hc(7)11ka2 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pc6/data6 pc5/data5 * v ppe applies to mc68hc711ka4 and mc68hc711ka2 only.
mc68hc11ka4 motorola mc68hc11ka4ts/d 9 figure 3 mc68hc11ka4/mc68hc711ka4 block diagram cop periodic spi sci an0 port e an1 an2 an3 an4 an5 an6 an7 a/d converter mode control timer system cpu v rl v rh pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 port h ddr port h ph0 ph1 ph2 ph3 pd0 pd1 pd2 pd3 pd4 pd5 port d ddr port d miso mosi sck ss rxd txd modb/ moda/ 640 bytes eeprom 768 bytes ram interrupt pulse accumulator data bus pa0 port a ddr pa1 pa2 pa3 pa4 pa5 pa6 pa7 ic3 ic2 ic1 oc5/ic4/oc1 oc4/oc1 oc3/oc1 oc2/oc1 pai/oc1 oscillator interrupt logic clock logic pc0 port c ddr pc1 pc2 pc3 pc4 pc5 pc6 pc7 data0 data1 data2 data3 data4 data5 data6 data7 port c pf0 port f pf1 pf2 pf3 pf4 pf5 pf6 pf7 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 pb0 port b pb1 pb2 pb3 pb4 pb5 pb6 pb7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 port a r/w xirq /v ppe 1 irq reset xtal extal e xout 2 lir v stby port g ddr port g pg7 pwm pw4 pw3 pw2 pw1 v dd v ss av dd av ss (ka1, ka4, 24 kbytes rom/ (ka3, ka4) eprom 32 kbytes rom/ (ka2) eprom port b ddr port f ddr ka2) (ka0, ka1, ka3, ka4) 2 v dd v ss internal external notes: 1. v ppe applies to mc68hc711ka4 and mc68hc711ka2 only. 2. not bonded on 64-pin version. 1024 bytes ram (ka2) address bus v rh v rl av dd av ss
section page motorola mc68hc11ka4 10 mc68hc11ka4ts/d 1 introduction 1 1.1 features ...................................................................................................................................... 1 2 operating modes and on-chip memory 11 2.1 operating modes ....................................................................................................................... 11 2.2 on-chip memory ....................................................................................................................... 11 3 erasable programmable read-only memory 21 4 electrically erasable programmable read-only memory 23 5 resets and interrupts 26 6 parallel input/output 31 7 serial communications interface 37 8 serial peripheral interface 44 9 analog-to-digital converter 48 10 main timer 52 10.1 real-time interrupt ................................................................................................................... 58 11 pulse accumulator 59 12 pulse-width modulation timer 62 table of contents
mc68hc11ka4 motorola mc68hc11ka4ts/d 11 2 operating modes and on-chip memory 2.1 operating modes in single-chip operating mode, the mc68hc11ka4 is a stand-alone microcontroller with no external ad- dress or data bus. in expanded non-multiplexed operating mode, the mcu can access a 64 kbyte physical address space. this space includes the same on-chip memory addresses used for single-chip mode, in addition to ad- dressing capabilities for external peripheral and memory devices. the expansion bus is made up of ports b, c, and f, and the r/w signal. in expanded operating mode, high order address bits are output on the port b pins, low order address bits on the port f pins, and the data bus on port c. the r/w pin controls the direction of data transfer on the port c bus. bootstrap mode allows special-purpose programs to be entered into internal ram. the bootloader pro- gram uses the serial communications interface (sci) to read a program of up to 768 bytes into on-chip ram. after a four-character delay, or after receiving the character for address $037f ($047f for mc68hc11ka2), control passes to the loaded program at $0080. special test mode is used primarily for factory testing. 2.2 on-chip memory the m68hc11 cpu is capable of addressing a 64 kbyte range. the init, init2, and config registers control the existence and locations of the registers, ram, eeprom, and rom in the physical 64 kbyte memory space. addressing beyond the 64 kbyte range is possible using a memory paging scheme in expanded mode only. the 128-byte register block originates at $0000 after reset and can be placed at any other 4 kbyte boundary ($x000) after reset by writing an appropriate value to the init register. the 768-byte ram (1024 bytes in the mc68hc11ka2) can be remapped to any 4 kbyte boundary in memory. the ram in the mc68hc11ka4 is divided into two sections of 128 bytes and 640 bytes. for the mc68hc11ka4, 128 bytes of the ram are mapped at $0000?007f unless the registers are mapped to this space. if the registers are located in this space, the same 128 bytes of ram are located at $0300 to $037f. the ram in the mc68hc11ka2 is divided into two sections of 128 bytes and 896 bytes. for the mc68hc11ka2, 128 bytes of the ram are mapped at $0000?007f unless the registers are mapped to this space. if the registers are located in this space, the same 128 bytes of ram are located at $0300 to $047f. remapping is accomplished by writing appropriate values into the two nibbles of the init register. refer to the register and ram mapping examples following the mc68hc11ka4 and mc68hc11ka2 memory maps. the 640-byte eeprom is initially located at $0d80 after reset, assuming eeprom is enabled in the memory map by the config register. eeprom can be placed at any other 4 kbyte boundary ($xd80) by writing appropriate values to the init2 register. the romad and romon control bits in the config register control the position and presence of rom/eprom in the memory map. in special test mode, the romon bit is forced to zero so that the rom/eprom is removed from the memory map. in single-chip mode, the romad bit is forced to one, causing the rom/eprom to be enabled at $a000?ffff ($8000?ffff in the mc68hc11ka2). this guarantees that there will be rom/eprom at the vector space.
motorola mc68hc11ka4 12 mc68hc11ka4ts/d figure 4 memory map for mc68hc11ka4 expanded 24 kbytes rom/eprom (note 3) (can be remapped to $2000?7fff or $a000?ffff by the config register) ffc0 ffff normal mode interrupt vectors 128-byte register block (can be remapped to any 4k page by the init register) 768 bytes ram (note 2) (can be remapped to any 4k page by the init register) single chip bootstrap special test ext ext ext $0000 $1000 $ffff 0000 007f 0d80 0fff a000 ffff bfc0 bfff special mode interrupt vectors ext boot rom (only present in bootstrap mode) be00 0080 037f 640 bytes eeprom (can be remapped to any 4k page by the init2 register) notes: $a000 1. eprom can be enabled in special test mode by setting the romon bit in the config register after reset. 2. 768 bytes ram in mc68hc711ka4, 1024 bytes ram in mc68hc711ka2. 3. 24 kbytes rom/eprom in mc68hc711ka4, 32 kbytes rom/eprom in mc68hc711ka2.
mc68hc11ka4 motorola mc68hc11ka4ts/d 13 figure 5 memory map for mc68hc11ka2 expanded 32 kbytes rom/eprom (note 3) (can be remapped to $0000?7fff or $8000?ffff by the config register) ffc0 ffff normal mode interrupt vectors 128-byte register block (can be remapped to any 4k page by the init register) 1024 bytes ram (note 2) (can be remapped to any 4k page by the init register) single chip bootstrap special test ext ext ext $0000 $1000 $ffff 0000 007f 0d80 0fff 8000 ffff bfc0 bfff special mode interrupt vectors ext boot rom (only present in bootstrap mode) be00 0080 047f 640 bytes eeprom (can be remapped to any 4k page by the init2 register) notes: $8000 1. eprom can be enabled in special test mode by setting the romon bit in the config register after reset. 2. 768 bytes ram in mc68hc711ka4, 1024 bytes ram in mc68hc711ka2. 3. 24 kbytes rom/eprom in mc68hc711ka4, 32 kbytes rom/eprom in mc68hc711ka2.
motorola mc68hc11ka4 14 mc68hc11ka4ts/d figure 6 ram and register mapping for mc68hc11ka4 figure 7 ram and register mapping for mc68hc11ka2 $0000 $007f $0080 $02ff $0300 $037f $12ff $1080 $0080 $02ff init = $00 reg @ $0000 ram @ $0080 init = $10 reg @ $0000 ram @ $1000 init = $04 reg @ $4000 ram @ $0000 ram b register block (128 bytes) (640 bytes) ram a (128 bytes) $0000 $007f register block (128 bytes) $1000 $107f ram a (128 bytes) ram b (640 bytes) $0000 $007f ram a (128 bytes) $4000 $407f register block (128 bytes) ram b (640 bytes) $0000 $007f $0080 $03ff $0400 $047f $13ff $1080 $0080 $03ff init = $00 reg @ $0000 ram @ $0080 init = $10 reg @ $0000 ram @ $1000 init = $04 reg @ $4000 ram @ $0000 ram b register block (128 bytes) (896 bytes) ram a (128 bytes) $0000 $007f register block (128 bytes) $1000 $107f ram a (128 bytes) ram b (896 bytes) $0000 $007f ram a (128 bytes) $4000 $407f register block (128 bytes) ram b (896 bytes)
mc68hc11ka4 motorola mc68hc11ka4ts/d 15 table 4 mc68hc11ka4 register and control bit assignments bit 7 654321 bit 0 $0000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $0001 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra $0002 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb $0003 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf $0004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $0005 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf $0006 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $0007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $0008 0 0 pd5 pd4 pd3 pd2 pd1 pd0 portd $0009 0 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd $000a pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $000b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $000c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $000d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $000e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $000f bit 7 654321 bit 0 tcnt (low) $0010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $0011 bit 7 654321 bit 0 tic1 (low) $0012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $0013 bit 7 654321 bit 0 tic2 (low) $0014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $0015 bit 7 654321 bit 0 tic3 (low) $0016 bit 15 14 13 12 11 10 9 bit 8 toc1(high) $0017 bit 7 654321 bit 0 toc1 (low) $0018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $0019 bit 7 654321 bit 0 toc2 (low) $001a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $001b bit 7 654321 bit 0 toc3 (low) $001c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $001d bit 7 654321 bit 0 toc4 (low) $001e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (high) $001f bit 7 654321 bit 0 ti4/o5 (low) $0020 om2 ol2 om3 ol3 om4 ol4 om5 ol5 tctl1 $0021 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a tctl2 $0022 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tmsk1 $0023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $0024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $0025 tof rtif paovf paif 0000 tflg2 $0026 0 paen pamod pedge 0 i4/o5 rtr1 rtr0 pactl $0027 bit 7 654321 bit 0 pacnt $0028 spie spe dwom mstr cpol cpha spr1 spr0 spcr $0029 spif wcol 0 modf 0000 spsr $002a bit 7 654321 bit 0 spdr $002b mbe 0 elat excol exrow 0 0 epgm eprog
motorola mc68hc11ka4 16 mc68hc11ka4ts/d $002c 0000 hppue gppue fppue bppue ppar $002d reserved $002e reserved $002f reserved $0030 ccf 0 scan mult cd cc cb ca adctl $0031 bit 7 654321 bit 0 adr1 $0032 bit 7 654321 bit 0 adr2 $0033 bit 7 654321 bit 0 adr3 $0034 bit 7 654321 bit 0 adr4 $0035 bulkp lvpen bprt4 ptcon bprt3 bprt2 bprt1 bprt0 bprot $0036 reserved $0037 ee3 ee2 ee1 ee0 0000 init2 $0038 lirdv cwom 0 irvne lsbf spr2 xdv1 xdv0 opt2 $0039 adpu csel irqe dly cme fcme cr1 cr0 option $003a bit 7 654321 bit 0 coprst $003b odd even lvpi byte row erase eelat eepgm pprog $003c rboot smod mda psel4 psel3 psel2 psel1 psel0 hprio $003d ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 init $003e tilop 0 occr cbyp disr fcm fcop 0 test1 $003f romad 1 clkx paren nosec nocop romon eeon config $0040 reserved to $005f reserved $0060 con34 con12 pcka2 pcka1 0 pckb3 pckb2 pckb1 pwclk $0061 pclk4 pclk3 pclk2 pclk1 ppol4 ppol3 ppol2 ppol1 pwpol $0062 bit 7 654321 bit 0 pwscal $0063 tpwsl discp 0 0 pwen4 pwen3 pwen2 pwen1 pwen $0064 bit 7 654321 bit 0 pwcnt1 $0065 bit 7 654321 bit 0 pwcnt2 $0066 bit 7 654321 bit 0 pwcnt3 $0067 bit 7 654321 bit 0 pwcnt4 $0068 bit 7 654321 bit 0 pwper1 $0069 bit 7 654321 bit 0 pwper2 $006a bit 7 654321 bit 0 pwper3 $006b bit 7 654321 bit 0 pwper4 $006c bit 7 654321 bit 0 pwdty1 $006d bit 7 654321 bit 0 pwdty2 $006e bit 7 654321 bit 0 pwdty3 $006f bit 7 654321 bit 0 pwdty4 $0070 btst bspl 0 sbr12 sbr11 sbr10 sbr9 sbr8 scbdh $0071 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 scbdl $0072 loops woms 0 m wake ilt pe pt sccr1 $0073 tie tcie rie ilie te re rwu sbk sccr2 $0074 tdre tc rdrf idle or nf fe pf scsr1 $0075 0000000raf scsr2 table 4 mc68hc11ka4 register and control bit assignments (continued) bit 7 654321 bit 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 17 *the reset values of rboot, smod, and mda depend on the mode selected at power up. rboot ?read bootstrap rom valid only when smod is set to one (bootstrap or special test mode). can only be written in special mode. 0 = bootloader rom disabled and not in map 1 = bootloader rom enabled and in map at $be00?bfff smod and mda ?pecial mode select and mode select a these two bits can be read at any time. smod can only be written to zero. mda can only be written once in normal modes or any time in special modes. psel[4:0] ?riority select bits [4:0] refer to 5 resets and interrupts . $0076 r8 t8 000000 scdrh $0077 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdrl $0078 reserved to $007b reserved $007c 0000ph3ph2ph1ph0 porth $007d 0000 ddh3 ddh2 ddh1 ddh0 ddrh $007e pg7 0000000 portg $007f ddg7 0000000 ddrg hprio ?highest priority i-bit interrupt and miscellaneous $003c bit 7 654321 bit 0 rboot* smod* mda* psel4 psel3 psel2 psel1 psel0 reset: 00000110 single chip 00100110 expanded 11000110 bootstrap 01100110 special test inputs latched at reset modb moda mode smod mda 1 0 single chip 0 0 1 1 expanded 0 1 0 0 bootstrap 1 0 0 1 special test 1 1 table 4 mc68hc11ka4 register and control bit assignments (continued) bit 7 654321 bit 0
motorola mc68hc11ka4 18 mc68hc11ka4ts/d can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode. ram[3:0] ?nternal ram map position specifies upper four bits of ram address. at reset, ram is mapped to $0000 along with register block. reg[3:0] ?28-byte register block map position specifies upper four bits of register space address. at reset, registers are mapped to $0000. config is made up of eeprom cells and static working latches. the operation of the mcu is con- trolled directly by these latches and not the actual eeprom byte. when programming the config reg- ister, the eeprom byte is being accessed. when the config register is being read, the static latches are being accessed. these bits can be read at any time. the value read is the one latched into the register from the ee- prom cells during the last reset sequence. a new value programmed into this register cannot be read until after a subsequent reset sequence. unused bits always read as ones. if smod = 1, config bits can be written at any time. if smod = 0 config bits can only be written using the eeprom programming sequence, and are neither readable nor active until latched via the next reset. romad ?rom/eprom mapping control in single-chip mode romad is forced to one out of reset. 0 = rom/eprom located at $2000?7fff ($2000?9fff in mc68hc11ka2) 1 = rom/eprom located at $a000?ffff ($8000?ffff in mc68hc11ka2) bit 6 ?not implemented always reads one clkx ?xout clock enable 0 = xout pin disabled 1 = x clock driven out on the xout pin paren ?pull-up assignment register enable refer to 6 parallel input/output . nosec ?security disable nosec is invalid unless the security mask option is specified before the mcu is manufactured. if se- curity mask option is omitted nosec always reads one. 0 = security enabled 1 = security disabled init ?am and i/o register mapping $003d bit 7 654321 bit 0 ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 reset: 0000000 0 config ?op, rom mapping, eeprom enables $003f bit 7 654321 bit 0 romad clkx paren nosec nocop romon eeon reset: 1
mc68hc11ka4 motorola mc68hc11ka4ts/d 19 nocop ?cop system disable resets to programmed value 0 = cop enabled (forces reset on time-out) 1 = cop disabled (does not force reset on time-out) romon ?rom/eprom enable in single-chip mode, romon is forced to one out of reset. in special test mode, romon is forced to zero out of reset. 0 = rom/eprom removed from memory map 1 = rom/eprom present in memory map eeon ?eeprom enable 0 = eeprom disabled from memory map 1 = eeprom present in memory map with location depending on value specified in ee[3:0] in init2 bit 7 ?not implemented always reads zero cwom ?port c wired-or mode refer to 6 parallel input/output . bit 5 ?not implemented always reads zero irvne ?internal read visibility/not e can be written at any time if smod = 1. if smod = 0, only one write is allowed. in expanded mode, irvne determines whether irv is on or off. in special test mode, irvne is reset to one. in all other modes, irvne is reset to zero. 0 = no internal read visibility on external bus 1 = data from internal reads is driven out of the external data bus. in single-chip modes, this bit determines whether the e clock drives out from the chip. 0 = e is driven out from the chip. 1 = e pin is driven low. lsbf ?spi lsb first enable refer to 8 serial peripheral interface . spr2 ?spi clock rate select refer to 8 serial peripheral interface . opt2 ?ystem configuration options 2 $0038 bit 7 654321 bit 0 cwom irvne lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0 mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne can be written single chip 0 on off e once expanded 0 on off irv once boot 0 on off e once special test 1 on on irv once
motorola mc68hc11ka4 20 mc68hc11ka4ts/d xdv[1:0] ?xout clock divide select these two bits control the frequency of the clock that is driven out the xout pin. the clkx bit in the config register controls whether this clock is on or off. when a clock rate is selected, allow a maxi- mum of 16 cycles for stabilization. during reset a frequency of extal is output. this frequency can be divided after reset. note that the phase relationship between the 4xdv1 signal and both extal and e cannot be predicted. refer to the following table for further information about xout frequencies. note the xout pin is not bonded in the 64-pin package. table 5 xout frequencies xdv[1:0] extal divided by frequency at extal = 8 mhz frequency at extal = 12 mhz frequency at extal = 16 mhz 0 0 1 8 mhz 12 mhz 16 mhz 0 1 4 2 mhz 3 mhz 4 mhz 1 0 6 1.33 mhz 2 mhz 2.7 mhz 1 1 8 1 mhz 1.5 mhz 2 mhz xdv[1:0] extal divided by frequency at extal = 8.4 mhz frequency at extal = 12.6 mhz frequency at extal = 16.8 mhz 0 0 1 8.4 mhz 12.6 mhz 16.8 mhz 0 1 4 2.1 mhz 3.15 mhz 4.2 mhz 1 0 6 1.4 mhz 2.1 mhz 2.8 mhz 1 1 8 1.05 mhz 1.57 mhz 2.1 mhz
mc68hc11ka4 motorola mc68hc11ka4ts/d 21 3 erasable programmable read-only memory the mc68hc711ka4 has 24 kbytes of rom/eprom. the mc68hc711ka2 has 32 kbytes of rom/ eprom. in all parts, the rom/eprom can be mapped to one of two locations in the memory map. the locations are as follows: in the mc68hc11ka4, the rom/eprom can be mapped at $2000?7fff or $a000?ffff. if it is mapped to $a000?ffff, vector space is included. in single-chip mode the mc68hc11ka4 rom/ eprom is forced to $a000?ffff (romad = 1) and enabled (romon = 1), regardless of the value in the config register. in the mc68hc11ka2, the rom/eprom can be mapped at $0000?7fff or $8000?ffff. if it is mapped to $8000?ffff, vector space is included. in single-chip mode the mc68hc11ka2 rom/ eprom is forced to $8000?ffff (romad = 1) and enabled (romon = 1), regardless of the value in the config register. in prog mode, the eprom/otprom is programmed as a stand-alone eprom by adapting the mcu footprint to the 27256-type eprom and using an appropriate eprom programmer. programming eprom/otprom requires an external 12.25 volt nominal power supply (v ppe ). there are two meth- ods that can be used to program and verify eprom/otprom. in normal mcu mode, eprom/otprom can be programmed in any operating mode ?pecial test, bootstrap, expanded, or single chip. normal programming is completed using the eprog register. to program the eprom, complete the following steps using the eprog register: 1. write to eprog with the elat bit set. 2. write data to the desired address. 3. write to eprog with the elat and epgm bits set. 4. delay for 10 ms or more, as appropriate. 5. clear the epgm bit in eprog to turn off the v ppe voltage. 6. clear the eprog register to reconfigure the eprom address and data buses for normal op- eration. mbe ?multiple byte program enable used for factory test purposes only bit 6 ?not implemented always reads zero elat ?eprom latch control if elat = 1, eprom is in programming mode and cannot be read. if elat = 1, writes to eprom cause address and data to be latched. 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming excol ?select extra columns used for factory test purposes only exrow ?select extra row used for factory test purposes only bits [2:1] ?not implemented always read zero eprog ?prom programming control $002b bit 7 654321 bit 0 mbe elat excol exrow epgm reset: 0000000 0
motorola mc68hc11ka4 22 mc68hc11ka4ts/d epgm ?eprom program command if elat = 1 then epgm = 0. 0 = programming power to eprom array switched off 1 = power to eprom array switched on figure 8 wiring diagram for mc68hc711ka4/ka2 eprom in prog mode notes: pf4/addr4 pf5/addr5 pf6/addr6 pf1/addr1 pf2/addr2 pf3/addr3 pf7/addr7 pf0/addr0 addr4 addr5 addr6 addr1 addr2 addr3 addr7 addr12 addr8 addr9 addr10 addr11 addr0 pb6/addr14 pb4/addr12 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pc7/data7 pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 pc1/data1 pc0/data0 o7 o6 o5 o1 o2 o4 o3 o0 addr4 addr5 addr6 addr1 addr2 addr3 addr7 addr12 addr8 addr9 addr10 addr11 addr0 addr14 o7 o6 o5 o1 o2 o4 o3 o0 internal 24 kbyte (32 kbytes, ka2) eprom pin functions mcu pin functions eprom mode pin connections mc68hc711ka4 irq xirq /v ppe pb7/addr15 ce oe pb5/addr13 addr13 addr13 gnd gnd pa0/ic3 pa3/ic4/oc5/oc1 v ss ce oe v cc v pp pe0/an0 addr14 gnd pa1/ic2 gnd pa2/ic1 gnd pa4/oc4/oc1 gnd pa5/oc3/oc1 gnd pa6/oc2/oc1 gnd pa7/pai/oc1 gnd pg7/r/w gnd pd0/rxd gnd pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss unused gnd gnd gnd gnd v rl v rh extal xtal e moda/lir modb/v stby reset gnd gnd gnd unused gnd ph0/pw1 ph1/pw2 ph2/pw3 ph3/pw4 testxx (3) xout pe1/an1 pe2/an2 pe3/an3 pe4/an4 pe5/an5 pe6/an6 pe7/an7 gnd gnd gnd gnd gnd gnd v ss v ss v dd v cc v pp outputs inputs note 3 note 4 note 1 note 2 note 1 note 4 1. unused inputs ?grounding is recommended. 2. unused inputs ?these pins may be left unterminated. 3. unused outputs ?these pins should be left unconnected. 4. grounding these six pins configures the mc68hc711ka4/ka2 for eprom emulation mode. eprom 27256 footprint mc68hc711ka2
mc68hc11ka4 motorola mc68hc11ka4ts/d 23 4 electrically erasable programmable read-only memory the 640-byte on-chip eeprom is initially located from $0d80 to $0fff after reset in all modes. it can be mapped to any other 4 kbyte boundary by writing to the init2 register. the eeprom is enabled by the eeon bit in the config register. programming and erasing is controlled by the pprog register. an internal oscillator clock-run charge pump supplies the programming voltage. use of the block protect register (bprot) prevents inadvertent writes to (or erases of) blocks of eeprom. the csel bit in the option register selects the on-chip oscillator clock for programming and erasing while operating at fre- quencies below 1 mhz. refer to 5 resets and interrupts . in special mode there is an extra row of 16 bytes of eeprom (located at $0d60), which is used for factory testing. endurance and data retention specifications do not apply to this row. the erased state of eeprom is $ff (all ones). to erase the eeprom, ensure that the proper bits of the bprot register are cleared, then complete the following steps using the pprog register: 1. write to pprog with the erase, eelat, and appropriate byte and row bits set. 2. write to the appropriate eeprom address with any data. row erase only requires a write to any location in the row. bulk erase is accomplished by writing to any location in the array. 3. write to pprog with erase, eelat, eepgm, and the appropriate byte and row bits set. 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the high voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. to program the eeprom, ensure the proper bits of the bprot register are cleared, then complete the following steps using the pprog register: 1. write to pprog with the eelat bit set. 2. write data to the desired address. 3. write to pprog with the eelat and eepgm bits set. 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the high voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. caution since it is possible to perform other operations while the eeprom programming/ erase operation is in progress, it is fairly common to start the operation then return to the main program until the 10 ms is completed. when the eelat bit is set at the beginning of a program/erase operation, the eeprom is electronically removed from the memory map; thus, it is not accessible during the program/erase cycle. care must be taken to ensure that eeprom resources will not be needed by any routines in the code during the 10 ms program/erase time.
motorola mc68hc11ka4 24 mc68hc11ka4ts/d note block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special mode. block protect register bits can be written to one (protection enabled) at any time. bulkp ?bulk erase of eeprom protect 0 = eeprom can be bulk erased normally 1 = eeprom cannot be bulk or row erased lvpen ?low voltage programming protect enable if lvpen = 1, programming of the eeprom is enabled unless the lvpi circuit detects that v dd has fallen below a safe operating voltage thus setting the low voltage programming inhibit bit in pprog reg- ister (lvpi = 1). 0 = low voltage programming protect for eeprom disabled 1 = low voltage programming protect for eeprom enabled bprt[4:0] ?lock protect bits for eeprom 0 = protection disabled 1 = protection enabled ptcon ?protect for config 0 = config register can be programmed or erased normally 1 = config register cannot be programmed or erased init2 can be written only once in normal modes, any time in special modes. ee[3:0] ?eeprom map position eeprom is at $xd80?xfff, where x is the hexadecimal digit represented by ee[3:0] bits. bits [3:0] ?not implemented always read zero bprot ?lock protect $0035 bit 7 654321 bit 0 bulkp lvpen bprt4 ptcon bprt3 bprt2 bprt1 bprt0 reset: 1111111 1 bit name block protected block size bprt4 $xf80?xfff 128 bytes bprt3 $xe60?xf7f 288 bytes bprt2 $xde0?xe5f 128 bytes bprt1 $xda0?xddf 64 bytes bprt0 $xd80?xd9f 32 bytes init2 ?eprom mapping $0037 bit 7 654321 bit 0 ee3 ee2 ee1 ee0 reset: 0000000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 25 odd ?program odd rows in half of eeprom (test) even ?program even rows in half of eeprom (test) lvpi ?low voltage programming inhibit lvpi can be read at any time and writes to lvpi have no meaning nor effect. lvpi is set if lvpen bit in bprot register equals 1 and the lvpi circuit detects that v dd has fallen below a safe operating volt- age. once set, lvpi is cleared when v dd returns to a safe operating voltage or if lvpen bit in bprot register is cleared. if lvpen = 0, then lvpi is always zero and has no meaning nor effect. 0 = eeprom programming enabled 1 = eeprom programming disabled byte ?byte/other eeprom erase mode 0 = row or bulk erase mode used 1 = erase only one byte of eeprom row ?row/all eeprom erase mode (only valid when byte = 0) 0 = all 640 bytes of eeprom erased 1 = erase only one 16-byte row of eeprom erase ?erase/normal control for eeprom 0 = normal read or program mode 1 = erase mode eelat ?eeprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bus configured for programming or erasing eepgm ?eeprom program command 0 = program or erase voltage switched off to eeprom array 1 = program or erase voltage switched on to eeprom array refer also to init2 register. pprog ?eeprom programming control $003b bit 7 654321 bit 0 odd even lvpi byte row erase eelat eepgm reset: 0000000 0 byte row action 0 0 bulk erase (all 640 bytes) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase
motorola mc68hc11ka4 26 mc68hc11ka4ts/d 5 resets and interrupts the mc68hc11ka4/ka2 has three reset vectors and 18 interrupt vectors. the reset vectors are as fol- lows: ?reset , or power-on reset ?clock monitor fail ?cop failure the 18 interrupt vectors service 22 interrupt sources (three non-maskable, 19 maskable). the three nonmaskable interrupt vectors are as follows: ?xirq pin (x-bit interrupt) ?illegal opcode trap ?software interrupt on-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter- rupt mask bit (i) in the condition code register (ccr) is clear. maskable interrupts are prioritized accord- ing to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (hprio). the hprio register can be written at any time, provided bit i in the ccr is set. nineteen interrupt sources in the mc68hc11ka4/ka2 are subject to masking by the global interrupt mask bit (bit i in the ccr). in addition to the global bit i, all of these sources, except the external interrupt (irq ) pin, are controlled by local enable bits in control registers. most interrupt sources in the m68hc11 have separate interrupt vectors; therefore, there is usually no need for software to poll control registers to determine the cause of an interrupt. for some interrupt sources, such as the sci interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. for example, the rdrf flag in the sci system is cleared by the automatic clearing mechanism consisting of a read of the sci status register while rdrf is set, followed by a read of the sci data register. the normal response to an rdrf interrupt request would be to read the sci status register to check for receive errors, then to read the received data from the sci data register. these two steps satisfy the automatic clearing mechanism without re- quiring any special instructions. refer to the following table for a list of interrupt and reset vector assignments
mc68hc11ka4 motorola mc68hc11ka4ts/d 27 *can be written only once in first 64 cycles out of reset in normal mode, or at any time in special mode. adpu ?/d converter power-up refer to 9 analog-to-digital converter . csel ?lock select refer to 9 analog-to-digital converter . irqe ?rq select edge sensitive only 0 = low level recognition 1 = falling edge recognition vector address interrupt source ccr mask bit local mask ffc0, c1 ?ffd4, d5 reserved ffd6, d7 sci serial system i sci receive data register full rie sci receiver overrun rie sci transmit data register empty tie sci transmit complete tcie sci idle line detect ilie ffd8, d9 spi serial transfer complete i spie ffda, db pulse accumulator input edge i paii ffdc, dd pulse accumulator overflow i paovi ffde, df timer overflow i toi ffe0, e1 timer input capture 4/output compare 5 i i4/o5i ffe2, e3 timer output compare 4 i oc4i ffe4, e5 timer output compare 3 i oc3i ffe6, e7 timer output compare 2 i oc2i ffe8, e9 timer output compare 1 i oc1i ffea, eb timer input capture 3 i ic3i ffec, ed timer input capture 2 i ic2i ffee, ef timer input capture 1 i ic1i fff0, f1 real-time interrupt i rtii fff2, f3 irq i none fff4, f5 xirq pin x none fff6, f7 software interrupt none none fff8, f9 illegal opcode trap none none fffa, fb cop failure none nocop fffc, fd clock monitor fail none cme fffe, ff reset none none option ?ystem configuration options $0039 bit 7 654321 bit 0 adpu csel irqe* dly cme fcme* cr1* cr0* reset: 0001000 0
motorola mc68hc11ka4 28 mc68hc11ka4ts/d dly ?nable oscillator start-up delay on exit from stop 0 = no stabilization delay on exit from stop 1 = stabilization delay enabled on exit from stop cme ?clock monitor enable 0 = clock monitor disabled; slow clocks can be used 1 = slow or stopped clocks cause clock failure reset fcme ?force clock monitor enable 0 = clock monitor follows the state of the cme bit 1 = clock monitor circuit is enabled until next reset cr[1:0] ?cop timer rate select write $55 to coprst to arm cop watchdog clearing mechanism. write $aa to coprst to reset cop watchdog. *rboot, smod, and mda reset depend on power-up initialization mode and can only be written in special mode. rboot ?read bootstrap rom refer to 2 operating modes and on-chip memory . smod ?special mode select refer to 2 operating modes and on-chip memory . mda ?mode select a refer to 2 operating modes and on-chip memory . table 6 cop timer rate select cr[1:0] divide e/2 15 by xtal = 8.0 mhz time-out ?/+16.4 ms xtal = 12.0 mhz time-out ?/+10.9 ms xtal = 16.0 mhz time-out ?/+8.2 ms 0 0 0 1 16.384 ms 10.923 ms 8.192 ms 0 0 1 4 65.536 ms 43.691 ms 32.768 ms 0 1 0 16 262.14 ms 174.76 ms 131.07 ms 0 1 1 64 1.049 s 699.05 ms 524.29 ms e = 2.0 mhz 3.0 mhz 4.0 mhz coprst ?arm/reset cop timer circuitry $003a bit 7 654321 bit 0 7654321 0 reset: 0000000 0 hprio ?highest priority i-bit interrupt and miscellaneous $003c bit 7 654321 bit 0 rboot* smod* mda* psel4 psel3 psel2 psel1 psel0 reset: 0011 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 29 psel[4:0] ?priority select bits [4:0] can be written only while bit i in the ccr is set (interrupts disabled). these bits select one interrupt source to be elevated above all other i-bit related sources. config is made up of eeprom cells and static latches. the operation of the mcu is controlled directly by these latches and not the actual eeprom byte. when programming the config register, the ee- prom byte is being accessed. when the config register is being read, the static latches are being accessed. these bits can be read at any time. the value read is the one latched into the register from the ee- prom cells during the last reset sequence. a new value programmed into this register cannot be read until after a subsequent reset sequence. unused bits always read as ones. if smod = 1, config bits can be written at any time. if smod = 0 config bits can only be written using the eeprom programming sequence, and are neither readable nor active until latched via the next reset. romad ?rom/eprom mapping control refer to 2 operating modes and on-chip memory . pselx interrupt source promoted 43210 0 0 0 x x reserved (default to irq ) 00100 reserved (default to irq ) 00101 reserved (default to irq ) 00110irq 00111 real-time interrupt 01000 timer input capture 1 01001 timer input capture 2 01010 timer input capture 3 01011 timer output compare 1 01100 timer output compare 2 01101 timer output compare 3 01110 timer output compare 4 01111 timer input capture 4/output compare 5 10000 timer overflow 10001 pulse accumulator overflow 10010 pulse accumulator input edge 10011 spi serial transfer complete 10100 sci serial system 10101 reserved (default to irq ) 10110 reserved (default to irq ) 10111 reserved (default to irq ) 1 1 x x x reserved (default to irq ) config ?cop, rom mapping, eeprom enables $003f bit 7 654321 bit 0 romad clkx paren nosec nocop romon eeon reset: 1
motorola mc68hc11ka4 30 mc68hc11ka4ts/d bit 6 ?not implemented always reads one clkx ?xout clock refer to 2 operating modes and on-chip memory . paren ?pull-up assignment register enable refer to 6 parallel input/output . nosec ?security disable refer to 2 operating modes and on-chip memory . nocop ?cop system disable resets to programmed value 0 = cop enabled (forces reset on time-out) 1 = cop disabled (does not force reset on time-out) romon ?rom/eprom enable refer to 2 operating modes and on-chip memory . eeon ?eeprom enable refer to 2 operating modes and on-chip memory .
mc68hc11ka4 motorola mc68hc11ka4ts/d 31 6 parallel input/output the mc68hc11ka4/ka2 has up to 51 input/output lines, depending on the operating mode. to en- hance the i/o functions, the data bus of this microcontroller is non-multiplexed. the following table is a summary of the configuration and features of each port. * only four pins on 64-pin version. romad ?rom mapping control refer to 2 operating modes and on-chip memory . bit 6 ?not implemented always reads one clkx ?xout clock enable refer to 2 operating modes and on-chip memory . paren ?pull-up assignment register enable 0 = pull-ups always disabled regardless of state of bits in ppar 1 = pull-ups either enabled or disabled through ppar nosec ?security disable refer to 2 operating modes and on-chip memory . nocop ?cop system disable refer to 5 resets and interrupts . romon ?rom/eprom enable refer to 2 operating modes and on-chip memory . eeon ?eeprom enable refer to 2 operating modes and on-chip memory . port input pins output pins bidirectional pins shared functions port a 8 timer port b 8 high order address port c 8 data bus port d 6 sci and spi port e 8* a/d converter port f 8 low order address port g 1 r/w signal port h 4 pwms config ?cop, rom mapping, eeprom enables $003f bit 7 654321 bit 0 romad clkx paren nosec nocop romon eeon reset: 1
motorola mc68hc11ka4 32 mc68hc11ka4ts/d lirdv ?lir driven refer to 2 operating modes and on-chip memory . cwom ?port c wired-or mode 0 = port c operates normally. 1 = port c outputs are open-drain. bit 5 ?not implemented always reads zero irvne ?internal read visibility/not e refer to 2 operating modes and on-chip memory . lsbf ?spi lsb first enable refer to 8 serial peripheral interface . spr2 ?spi clock (sck) rate select refer to 8 serial peripheral interface . xdv1, xdv0 ?xout clock divide select refer to 2 operating modes and on-chip memory . note do not confuse pin function with the electrical state of the pin at reset. all general- purpose i/o pins configured as inputs at reset are in a high-impedance state and the contents of port data registers is undefined. in port descriptions, a ??indicates this condition. the pin function is mode dependent. note to enable pa3 as fourth input capture, set the i4/o5 bit in the pactl register. oth- erwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the dda3 bit is set (configuring pa3 as an output), and ic4 is enabled, writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/o5 register is acting as ic4. pa7 drives the pulse ac- cumulator input but also can be configured for general-purpose i/o, or output com- pare. note that even when pa7 is configured as an output, the pin still drives the pulse accumulator input. opt2 ?ystem configuration options 2 $0038 bit 7 654321 bit 0 lirdv cwom irvne lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0 porta ?ort a data $0000 bit 7 654321 bit 0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: uuuuuuu u alt. pin func.: pai oc2 oc3 oc4 ic4/oc5 ic1 ic2 ic3 and/or: oc1 oc1 oc1 oc1 oc1
mc68hc11ka4 motorola mc68hc11ka4ts/d 33 dda[7:0] ?ata direction for port a 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output reset state is mode dependent. in single-chip or bootstrap modes, port b pins are high impedance in- puts with selectable internal pull-up resistors. in expanded or test modes, port b pins are high order ad- dress outputs and portb is not in the memory map. ddb[7:0] ?data direction for port b 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output reset state is mode dependent. in single-chip or bootstrap modes, port f pins are high-impedance in- puts with selectable internal pull-up resistors. in expanded or test modes, port f pins are low order ad- dress outputs and portf is not in the memory map. ddra ?data direction register for port a $0001 bit 7 654321 bit 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 reset: 0000000 0 portb ?ort b data $0004 bit 7 654321 bit 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 s. chip or boot: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: uuuuuuu u expan. or test: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 ddrb ?data direction register for port b $0002 bit 7 654321 bit 0 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 reset: 0000000 0 portf ?port f data $0005 bit 7 654321 bit 0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 s. chip or boot: pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: uuuuuuu u expan. or test: addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0
motorola mc68hc11ka4 34 mc68hc11ka4ts/d ddf[7:0] ?data direction for port f 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output reset state is mode dependent. in single-chip or bootstrap modes, port c pins are high-impedance in- puts. it is customary to have an external pull-up resistor on lines that are driven by open-drain devices. in expanded or test modes, port c pins are data bus inputs and outputs and portc is not in the mem- ory map. ddc[7:0] ?data direction for port c 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output ddrf ?ata direction register for port f $0003 bit 7 654321 bit 0 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0000000 0 portc ?ort c data $0006 bit 7 654321 bit 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 s. chip or boot: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0000000 0 expan. or test: data7 data6 data5 data4 data3 data2 data1 data0 ddrc ?data direction register for port c $0007 bit 7 654321 bit 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 reset: 0000000 0 portd ?port d data $0008 bit 7 654321 bit 0 0 0 pd5 pd4 pd3 pd2 pd1 pd0 reset: 0 0 uuuuu u alt. pin func.: ss sck mosi miso txd rxd
mc68hc11ka4 motorola mc68hc11ka4ts/d 35 bits [7:6] ?ot implemented always read zero ddd[5:0] ?data direction for port d 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output note when the spi system is in slave mode, ddd5 has no meaning nor effect. when the spi system is in master mode, ddd5 determines whether bit 5 of portd is an error detect input (ddd5 = 0) or a general-purpose output (ddd5 = 1). if the spi system is enabled and expects any of bits [4:2] to be an input that bit will be an input regardless of the state of the associated ddr bit. if any of bits [4:2] are expected to be outputs that bit will be an output only if the associated ddr bit is set. *not bonded on 64-pin version. bits [7:4] ?not implemented always read zero xppue ?port x pin pull-up enable refer to paren bit in config register discussed in 6 parallel input/output . 0 = port x pin on-chip pull-up devices disabled 1 = port x pin on-chip pull-up devices enabled note fppue and bppue do not apply in expanded mode because ports f and b are address outputs. ddrd ?data direction register for port d $0009 bit 7 654321 bit 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 reset: 0000000 0 porte ?port e data $000a bit 7 654321 bit 0 pe7* pe6* pe5* pe4* pe3 pe2 pe1 pe0 reset: uuuuuuu u alt. pin func.: an7 an6 an5 an4 an3 an2 an1 an0 ppar ?ort pull-up assignment $002c bit 7 654321 bit 0 hppue gppue fppue bppue reset: 0000111 1
motorola mc68hc11ka4 36 mc68hc11ka4ts/d port h pins reset to high-impedance inputs with selectable internal pull-up resistors. bits [7:4] ?not implemented always read zero ddh[3:0] ?data direction for port h 0 = bits set to zero to configure corresponding i/o pin for input only 1 = bits set to one to configure corresponding i/o pin for output note in any mode, pwm circuitry forces the i/o state to be an output for each port h line associated with an enabled pulse-width modulator channel. in these cases, data direction bits are not changed and have no effect on these lines. ddrh reverts to controlling the i/o state of a pin when the associated function is disabled. refer to 12 pulse-width modulation timer for further information. port g pins reset to high-impedance inputs with selectable internal pull-up resistors. in expanded and special test modes pg7 becomes r/w . ddg7 ?data direction for port g 0 = bit set to zero to configure corresponding i/o pin for input only 1 = bit set to one to configure corresponding i/o pin for output in expanded and test modes, bit 7 is configured for r/w , forcing the state of this pin to be an output although the ddrg value remains zero. bits [6:0] ?not implemented always read zero porth ?port h data $007c bit 7 654321 bit 0 ph3ph2ph1ph0 reset: 0000uuuu alt. pin func.: pw4pw3pw2pw1 ddrh ?data direction register for port h $007d bit 7 654321 bit 0 ddh3 ddh2 ddh1 ddh0 reset: 0000111 1 portg ?port g data $007e bit 7 654321 bit 0 pg7 reset: u 000000 0 alt. pin func.: r/w ddrg ?data direction register for port g $007f bit 7 654321 bit 0 ddg7 reset: 0000000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 37 7 serial communications interface the sci, a universal asynchronous receiver transmitter (uart) serial communications interface, is one of two independent serial i/o subsystems in the mc68hc11ka4/ka2. rearranging registers and con- trol bits used in previous m68hc11 family devices has enhanced the existing sci system and added new features, which include the following: ?a 13-bit modulus prescaler that allows greater baud rate control ?a new idle mode detect, independent of preceding serial data ?a receiver active flag ?hardware parity for both transmitter and receiver the enhanced baud rate generator is shown in the following diagram. refer to the table of sci baud rate control values for standard values. figure 9 sci baud generator circuit diagram sci baud generator ? 3 ? 4 ? 13 oscillator and clock generator ( ? 4) xtal extal e as internal bus clock (ph2) 1:1 scp[1:0] 1:0 0:1 0:0 ? 2 0:0:0 ? 2 0:0:1 ? 2 0:1:0 ? 2 0:1:1 ? 2 1:0:0 ? 2 1:0:1 ? 2 1:1:0 1:1:1 ? 16 sci receive baud rate (16x) scr[2:0] sci transmit baud rate (1x)
motorola mc68hc11ka4 38 mc68hc11ka4ts/d figure 10 sci transmitter block diagram fe nf or idle rdrf tc tdre scsr interrupt status sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1/ txd scdr tx buffer transfer tx buffer shift enable jam enable preamble?am 1's break?am 0's (write-only) force pin direction (out) size 8/9 wake m r8 sccr1 sci control 1 pe ilt pt parity generator transmitter baud rate clock
mc68hc11ka4 motorola mc68hc11ka4ts/d 39 figure 11 sci receiver block diagram fe nf or idle rdrf tc tdre scsr1 sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m woms loops wake-up logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0/ rxd scdr rx buffer stop (8)76543210 10 (11) - bit rx shift register (read-only) sccr1 sci control 1 rie rdrf start msb all ones data recovery ? 16 rwu re m disable driver pe ilt pt pf raf parity detect scsr2 sci status 2 receiver baud rate clock
motorola mc68hc11ka4 40 mc68hc11ka4ts/d btst ?baud register test (test) bspl ?baud rate counter split (test) bit 5 ?not implemented always reads zero sbr[12:0] ?sci baud rate selects use the following formula to calculate sci baud rate. refer to the table of baud rate control values for example rates: sci baud rate = extal ? [16 (2 br)] where br is the contents of scbdh, l (br = 1, 2, 3, ..., 8191). br = 0 disables the baud rate generator. loops ?sci loop mode enable 0 = sci transmit and receive operate normally 1 = sci transmit and receive are disconnected from txd and rxd pins, and transmitter output is fed back into the receiver input scbdh/l ?ci baud rate control high/low $0070, $0071 bit 7 654321 bit 0 $0070 btst bspl sbr12 sbr11 sbr10 sbr9 sbr8 high reset: 00000000 $0071 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 low reset: 00000100 table 7 sci baud rate control values target crystal frequency (extal) baud 8 mhz 12 mhz 16 mhz rate dec value hex value dec value hex value dec value hex value 110 2272 $08e0 3409 $0d51 4545 $11c1 150 1666 $0682 2500 $09c4 3333 $0d05 300 833 $0341 1250 $04e2 1666 $0682 600 416 $01a0 625 $0271 833 $0341 1200 208 $00d0 312 $0138 416 $01a0 2400 104 $0068 156 $009c 208 $00d0 4800 52 $0034 78 $004e 104 $0068 9600 26 $001a 39 $0027 52 $0034 19.2 k 13 $000d 20 $0014 26 $001a 38.4 k 13 $000d sccr1 ?ci control 1 $0072 bit 7 654321 bit 0 loops woms m wake ilt pe pt reset: 0000000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 41 woms ?wired-or mode for sci pins (pd1, pd0; see also dwom bit in spcr.) 0 = txd and rxd operate normally 1 = txd and rxd are open drains if operating as an output bit 5 ?not implemented always reads zero m ?mode (select character format) 0 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ?wakeup by address mark/idle 0 = wakeup by idle line recognition 1 = wakeup by address mark (most significant data bit set) ilt ?idle line type 0 = short (sci counts consecutive ones after start bit) 1 = long (sci counts ones only after stop bit) pe ?parity enable 0 = parity disabled 1 = parity enabled pt ?parity type 0 = parity even (even number of ones causes parity bit to be zero, odd number of ones causes par- ity bit to be one) 1 = parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity bit to be one) tie ?transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ?transmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ?receiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ?idle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ?transmitter enable 0 = transmitter disabled 1 = transmitter enabled sccr2 ?ci control 2 $0073 bit 7 654321 bit 0 tie tcie rie ilie te re rwu sbk reset: 0000000 0
motorola mc68hc11ka4 42 mc68hc11ka4ts/d re ?receiver enable 0 = receiver disabled 1 = receiver enabled rwu ?receiver wakeup control 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ?send break 0 = break generator off 1 = break codes generated as long as sbk = 1 tdre ?transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr1 with tdre set and then writing to scdr. 0 = scdr busy 1 = scdr empty tc ?transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr1 with tc set and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ?receive data register full flag once cleared, idle is not set again until the rxd line has been active and becomes idle again. rdrf is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr1 with rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle ?idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr1 with idle set and then reading scdr. 0 = rxd line is active 1 = rxd line is idle or ?overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr1 with or set and then reading scdr. 0 = no overrun 1 = overrun detected nf ?noise error flag nf is set if majority sample logic detects anything other than a unanimous decision. clear nf by reading scsr1 with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected scsr1 ?ci status register 1 $0074 bit 7 654321 bit 0 tdre tc rdrf idle or nf fe pf reset: 1100000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 43 fe ?framing error fe is set when a zero is detected where a stop bit was expected. clear the fe flag by reading scsr1 with fe set and then reading scdr. 0 = stop bit detected 1 = zero detected pf ?parity error flag pf is set if received data has incorrect parity. clear pf by reading scsr1 with pe set and then reading scdr. 0 = parity correct 1 = incorrect parity detected bits [7:1] ?not implemented always read zero raf ?receiver active flag (read only) 0 = a character is not being received 1 = a character is being received r8 ?receiver bit 8 ninth serial data bit received when sci is configured for a nine data bit operation. t8 ?transmitter bit 8 ninth serial data bit transmitted when sci is configured for a nine data bit operation. bits [5:0] ?not implemented always read zero r/t[7:0] ?receiver/transmitter data bits [7:0] sci data is double buffered in both directions. scsr2 ?ci status register 2 $0075 bit 7 654321 bit 0 raf reset: 0000000 0 scdrh/l ?ci data register high/low $0076, $0077 bit 7 654321 bit 0 $0076 r8 t8 scdrh (high) $0077 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdrl (low)
motorola mc68hc11ka4 44 mc68hc11ka4ts/d 8 serial peripheral interface the spi allows the mcu to communicate synchronously with peripheral devices and other micropro- cessors. data rates can be as high as 2 mbits per second when configured as a master and 4 mbits per second when configured as a slave (assuming 4 mhz bus speed). two control bits in opt2 allow the transfer of data either msb or lsb first and select an additional divide by four stage to be inserted before the spi baud rate clock divider. figure 12 spi block diagram spi block 2spr spr0 spr1 cpha cpol mstr dwom spe spie spi control register modf wcol spif spi status register 8/16-bit shift register read data buffer msb lsb internal data bus spi interrupt request mstr spe mstr dwom spe spr0 spi clock (master) spi control select divider internal mcu clock clock logic clock pin control logic s m s m m s miso pd2 mosi pd3 sck pd4 ss pd5 spr1 ? 2 ? 4 ? 16 ? 32 8 8 8
mc68hc11ka4 motorola mc68hc11ka4ts/d 45 spie ?serial peripheral interrupt enable 0 = spi interrupts disabled 1 = spi interrupts enabled spe ?serial peripheral system enable 0 = spi off 1 = spi on dwom ?port d wired-or mode option for spi pins pd[5:2] (see also woms bit in sccr1.) 0 = normal cmos outputs 1 = open-drain outputs mstr ?master mode select 0 = slave mode 1 = master mode cpol, cpha ?clock polarity, clock phase refer to spi transfer format. figure 13 spi transfer format spcr ?erial peripheral control register $0028 bit 7 654321 bit 0 spie spe dwom mstr cpol cpha spr1 spr0 reset: 000001uu spi transfer format 1 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb 1 2 3 5 4 slave cpha=1 transfer in progress master transfer in progress slave cpha=0 transfer in progress 1. ss asserted 2. master writes to spdr 3. first sck edge 4. spif set 5. ss negated sample input data out (cpha = 0) sample input data out (cpha = 1)
motorola mc68hc11ka4 46 mc68hc11ka4ts/d note this figure shows transmission order when lsbf = 0 default. if lsbf = 1, data is transferred in reverse order (lsb first). spr2, spr1 and spr0 ?spi clock rate selects (spr2 is located in opt2 register) spif ?spi transfer complete flag this flag is set when an spi transfer is complete (after eight sck cycles in a data transfer). clear this flag by reading spsr (with spif = 1), then access spdr data register. 0 = no spi transfer complete or spi transfer still in progress 1 = spi transfer complete wcol ?write collision this flag is set if the mcu tries to write data into spdr while an spi data transfer is in progress. clear this flag by reading spsr (wcol = 1), then access spdr. 0 = no write collision 1 = write collision bit 5 ?not implemented always reads zero modf ?mode fault (mode fault terminates spi operation) 0 = no mode fault 1 = mode fault (ss is pulled low while mstr = 1) bits [3:0] ?not implemented always read zero spi is double buffered in, single buffered out. spr[2:0] divide e clock by frequency at e = 2 mhz (baud) 0 0 0 2 1.0 mhz 0 0 1 4 500 khz 0 1 0 16 125 khz 0 1 1 32 62.5 khz 1 0 0 8 250 khz 1 0 1 16 125 khz 1 1 0 64 31.3 khz 1 1 1 128 15.6 khz spsr ?erial peripheral status register $0029 bit 7 654321 bit 0 spif wcol modf reset: 0000000 0 spdr ?pi data $002a bit 7 654321 bit 0 bit 7 654321 bit 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 47 lirdv?lir driven refer to 2 operating modes and on-chip memory . cwom ?port c wired-or mode refer to 6 parallel input/output . bit 5 ?not implemented always reads zero irvne ?internal read visibility/not e refer to 2 operating modes and on-chip memory . lsbf ?spi lsb first enable 0 = spi data transferred msb first 1 = spi data transferred lsb first spr2 ?spi clock (sck) rate select adds a divide by four prescaler to spi clock chain. refer to spcr register. xdv[1:0] ?xout clock divide select refer to 2 operating modes and on-chip memory . opt2 ?ystem configuration options 2 $0038 bit 7 654321 bit 0 lirdv cwom irvne lsbf spr2 xdv1 xdv0 reset: 0 0 0 0 0 0 0
motorola mc68hc11ka4 48 mc68hc11ka4ts/d 9 analog-to-digital converter the analog-to-digital (a/d) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. the mc68hc11ka4/ka2 a/d converter system is an 8-channel (four channels on 64-pin version), 8-bit, multiplexed-input, successive-approximation converter. it does not require external sample and hold circuits. the sample and hold time is 12 clock cycles. refer to fig- ure 15 . the clock source for the a/d converter's charge pump, like the clock source for the eeprom charge pump, is selected with the csel bit in the option register. when the e clock is slower than 1 mhz, the csel bit must be set to ensure that the successive approximation sequence for the a/d converter will be completed before any charge loss occurs. in the case of the eeprom, it is the efficiency of the charge pump that is affected. figure 14 a/d converter block diagram the a/d converter can operate in single or multiple conversion modes. multiple conversions are per- formed in sequences of four. sequences can be performed on a single channel or on a group of chan- nels. ea9 a/d block pe0 an0 pe1 an1 pe2 an2 pe3 an3 pe4 an4 pe5 an5 pe6 an6 pe7 an7 analog mux 8-bit capacitive dac with sample and hold successive approximation register and control adctl a/d control cb cc cd mult scan ccf ca adr1 a/d result 1 adr2 a/d result 2 adr3 a/d result 3 adr4 a/d result 4 result register interface result internal data bus v rh v rl
mc68hc11ka4 motorola mc68hc11ka4ts/d 49 pins av dd and av ss provide the supply voltage to the digital portion of the a/d converter. pins v rh and v rl provide the reference supply voltage inputs. a multiplexer allows the single a/d converter to select one of 16 analog input signals. refer to the a/d converter channel assignment bits cd?a description. the a/d converter control logic implements automatic conversion sequences on a selected channel four times or on a group of four channels once each. a write to the adctl register initiates conversions and, if made while a conversion is in process, a write to adctl also halts a conversion operation in progress. when the mult bit is zero, the a/d converter system is configured to perform four consecutive conver- sions on the single channel specified by the four channel-select bits (cd?a). when the mult bit is one, the a/d system is configured to perform conversions on each channel in the group of four channels specified by the cd and cc channel select bits. refer to table 8 . when the scan bit is zero, four conversions are performed in the desired channel group, once each, to fill the four result registers. when scan is one, conversions continue channel-by-channel in the de- sired group with the result registers being updated continually as new data becomes available. figure 15 timing diagram for a sequence of four a/d conversions figure 16 electrical model of an analog input pin (sample mode) 0 32 64 96 128 ?e cycles sample analog input successive approximation sequence msb 4 cycles bit 6 2 cyc bit 5 2 cyc bit 4 2 cyc bit 3 2 cyc bit 2 2 cyc bit 1 2 cyc lsb 2 cyc 2 cyc end repeat sequence, scan = 1 set cc flag convert first channel, update adr1 convert second channel, update adr2 convert third channel, update adr3 convert fourth channel, update adr4 12 e cycles write to adctl e clock a/d conversion tim diffusion/poly < 2 pf coupler 400 na junction leakage + ~20v ?~0.7v * * this analog switch is closed only during the 12-cycle sample time. v rl input + ~12v ?~0.7v protection device 4 k w dummy n-channel output device analog input pin ~ 20 pf dac capacitance analog input pin
motorola mc68hc11ka4 50 mc68hc11ka4ts/d ccf ?conversions complete flag ccf is set after an a/d conversion cycle and cleared when adctl is written. bit 6 ?not implemented always reads zero scan ?continuous scan control 0 = do four conversions and stop 1 = convert four channels in selected group continuously mult ?multiple channel/single channel control 0 = convert single channel selected 1 = convert four channels in selected group cd?a ?channel select d through a *used for factory testing adctl ?/d control/status $0030 bit 7 654321 bit 0 ccf scan mult cd cc cb ca reset: 0000000 0 table 8 a/d converter channel assignments channel select control bits channel result in adrx if cd cc cb ca signal mult = 1 0000 an0 adr1 0001 an1 adr2 0010 an2 adr3 0011 an3 adr4 0100 an4 adr1 0101 an5 adr2 0110 an6 adr3 0111 an7 adr4 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 v rh * adr1 1101 v rl * adr2 1110 (v rh )/2* adr3 1111 reserved* adr4 adr[4:1] ?/d results $0031?0034 $0031 bit 7 654321 bit 0 adr1 $0032 bit 7 654321 bit 0 adr2 $0033 bit 7 654321 bit 0 adr3 $0034 bit 7 654321 bit 0 adr4
mc68hc11ka4 motorola mc68hc11ka4ts/d 51 *can be written only once in first 64 cycles out of reset in normal modes, any time in special mode. adpu ?a/d converter power-up 0 = a/d converter powered down 1 = a/d converter powered up csel ?clock select 0 = a/d and eeprom use system e clock 1 = a/d and eeprom use internal rc clock source irqe ?irq select edge sensitive only refer to 5 resets and interrupts . dly ?enable oscillator start-up delay on exit from stop refer to 5 resets and interrupts . cme ?clock monitor enable refer to 5 resets and interrupts . fcme ?force clock monitor enable refer to 5 resets and interrupts . cr[1:0] ?cop timer rate select refer to 5 resets and interrupts . option ?ystem configuration options $0039 bit 7 654321 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0001000 0
motorola mc68hc11ka4 52 mc68hc11ka4ts/d 10 main timer the timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. a timer overflow function allows software to extend the system's timing capability beyond the counter's 16-bit range. the timer has three channels of input capture, four channels of output compare, and one channel that can be configured as a fourth input capture or a fifth output compare. in addition, the timing system in- cludes pulse accumulator and real-time interrupt (rti) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the cop. refer to 11 pulse accumulator and 10.1 real-time interrupt for further information about these func- tions. refer to the following table for a summary of the crystal-related frequencies and periods. table 9 timer summary xtal frequencies 8.0 mhz 12.0 mhz 16.0 mhz other rates control 2.0 mhz 3.0 mhz 4.0 mhz (e) bits 500 ns 333 ns 250 ns (1/e) pr[1:0] main timer count rates 0 0 1 count overflow 500 ns 32.768 ms 333 ns 21.845 ms 250 ns 16.384 ms (e/1) (e/2 16) 0 1 1 count overflow 2.0 m s 131.07 ms 1.333 m s 87.381 ms 1.0 m s 65.536 ms (e/4) (e/2 18 ) 1 0 1 count overflow 4.0 m s 262.14 ms 2.667 m s 174.76 ms 2.0 m s 131.07 ms (e/8) (e/2 19 ) 1 1 1 count overflow 8.0 m s 524.29 ms 5.333 m s 349.52 ms 4.0 m s 262.14 ms (e/16) (e/2 20 ) rtr[1:0] periodic (rti) interrupt rates 0 0 0 1 1 0 1 1 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms 2.048 ms 4.096 ms 8.192 ms 16.384 ms (e/2 13) (e/214 ) (e/2 15 ) (e/2 16 ) cr[1:0] cop watchdog time-out rates 0 0 0 1 1 0 1 1 16.384 ms 65.536 ms 262.14 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms 8.192 ms 32.768 ms 131.07 ms 524.28 ms (e/2 15) (e/217 ) (e/2 19 ) (e/2 21 ) time-out tolerance (? ms/+...) 16.4 ms 10.9 ms 8.192 ms (e/2 15 )
mc68hc11ka4 motorola mc68hc11ka4ts/d 53 figure 17 timer block diagram pa3 oc5/ ic4/ oc1 16-bit latch clk tic1 (hi) 16-bit comparator = ic3f oc2f oc3f i4/o5f tflg1 tmsk1 ic1f ic1i 3 ic2f ic2i 2 ic3i 1 oc4f i4/o5i 16-bit timer bus 16-bit free-running counter tcnt (hi) tof toi 9 pr1 pr0 prescaler?ivide by 1, 4, 8, or 16 i4/o5 oc1i 8 foc1 oc2i 7 foc2 oc3i 6 foc3 oc4i 5 foc4 4 foc5 status flags force output compare interrupt enables port a oc5 ic4 cforc 16-bit timer bus oc1f bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 pin functions tcnt (lo) pa2/ ic1 tic1 (lo) 16-bit latch clk tic2 (hi) tic2 (lo) 16-bit latch clk tic3 (hi) tic3 (lo) toc1 (hi) toc1 (lo) toc2 (hi) toc2 (lo) toc3 (hi) toc3 (lo) toc4 (hi) toc4 (lo) 16-bit latch clk ti4/o5 (hi) ti4/o5 (lo) 16-bit comparator = 16-bit comparator = 16-bit comparator = 16-bit comparator = mcu eclk interrupt requests (further qualified by i-bit in ccr) pin control pa7/ oc1/ pai pa6/ oc2/ oc1 pa5/ oc3/ oc1 pa4/ oc4/ oc1 pa1/ ic2 pa0/ ic3 to pulse accumulator taps for rti, cop watchdog and pulse accumulator
motorola mc68hc11ka4 54 mc68hc11ka4ts/d foc[5:1] ?force output comparison when the foc bit associated with an output compare circuit is set, the output compare circuit immedi- ately performs the action it is programmed to do when an output match occurs. 0 = not affected 1 = output x action occurs bits [2:0] ?not implemented always read zero set bit(s) to enable oc1 to control corresponding pin(s) of port a bits [2:0] ?not implemented always read zero if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] ?not implemented always read zero tcnt resets to $0000. in normal modes, tcnt is read-only. ticx not affected by reset cforc ?timer compare force $000b bit 7 654321 bit 0 foc1 foc2 foc3 foc4 foc5 reset: 0000000 0 oc1m ?output compare 1 mask $000c bit 7 654321 bit 0 oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 reset: 0000000 0 oc1d ?output compare 1 data $000d bit 7 654321 bit 0 oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 reset: 0000000 0 tcnt ?timer count $000e, $000f $000e bit 15 14 13 12 11 10 9 bit 8 high tcnt $000f bit 7 654321 bit 0 low tic1?ic3 ?imer input capture $0010?0015 $0010 bit 15 14 13 12 11 10 9 bit 8 high tic1 $0011 bit 7 654321 bit 0 low $0012 bit 15 14 13 12 11 10 9 bit 8 high tic2 $0013 bit 7 654321 bit 0 low $0014 bit 15 14 13 12 11 10 9 bit 8 high tic3 $0015 bit 7 654321 bit 0 low
mc68hc11ka4 motorola mc68hc11ka4ts/d 55 all tocx register pairs reset to ones ($ffff). this is a shared register and is either input capture 4 or output compare 5 depending on the state of bit i4/o5 in pactl. writes to ti4/o5 have no effect when this register is configured as input capture 4. all ti4/o5 register pairs reset to ones ($ffff). om[5:2] ?output mode ol[5:2] ?output level toc1?oc4 ?imer output compare $0016?001d $0016 bit 15 14 13 12 11 10 9 bit 8 high toc1 $0017 bit 7 654321 bit 0 low $0018 bit 15 14 13 12 11 10 9 bit 8 high toc2 $0019 bit 7 654321 bit 0 low $001a bit 15 14 13 12 11 10 9 bit 8 high toc3 $001b bit 7 654321 bit 0 low $001c bit 15 14 13 12 11 10 9 bit 8 high toc4 $001d bit 7 654321 bit 0 low ti4/o5 ?timer input capture 4/output compare 5 $001e, $001f $001e bit 15 14 13 12 11 10 9 bit 8 high $001f bit 7 654321 bit 0 low tctl1 ?timer control 1 $0020 bit 7 654321 bit 0 om2 ol2 om3 ol3 om4 ol4 om5 ol5 reset: 0000000 0 omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1 tctl2 ?timer control 2 $0021 bit 7 654321 bit 0 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a reset: 00000000
motorola mc68hc11ka4 56 mc68hc11ka4ts/d oc1i?c4i ?output compare x interrupt enable i4/o5i ?input capture 4 or output compare 5 interrupt enable ic1i?c3i ?input capture x interrupt enable note control bits in tmsk1 correspond bit for bit with flag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. clear flags by writing a one to the corresponding bit position(s). oc1f?c4f ?output compare x flag set each time the counter matches output compare x value i4/o5f ?input capture 4/output compare 5 flag set by ic4 or oc5, depending on which function was enabled by i4/o5 bit in pactl ic1f?c3f ?input capture x flag set each time a selected active edge is detected on the icx input line toi ?timer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = timer overflow interrupt enabled rtii ?real-time interrupt enable 0 = rtif interrupts disabled 1 = interrupt requested when rtif is set to one. table 10 timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge tmsk1 ?timer interrupt mask 1 $0022 bit 7 654321 bit 0 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i reset: 0000000 0 tflg1 ?timer interrupt flag 1 $0023 bit 7 654321 bit 0 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f reset: 0000000 0 tmsk2 ?imer interrupt mask 2 $0024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 0000000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 57 note control bits [7:4] in tmsk2 correspond bit for bit with flag bits [7:4] in tflg2. ones in tmsk2 enable the corresponding interrupt sources. paovi ?pulse accumulator overflow interrupt enable refer to 11 pulse accumulator . paii ?pulse accumulator interrupt enable refer to 11 pulse accumulator . bits [3:2] ?not implemented always read zero pr[1:0] ?timer prescaler select in normal modes, pr1 and pr0 can only be written once, and the write must occur within 64 cycles after reset. refer to 10.1 real-time interrupt for specific timing values. clear flags by writing a one to the corresponding bit position(s). tof ?timer overflow flag set when tcnt changes from $ffff to $0000 rtif ?real-time (periodic) interrupt flag set periodically. refer to rtr[1:0] bits in pactl register. paovf ?pulse accumulator overflow flag refer to 11 pulse accumulator . paif ?pulse accumulator input edge flag refer to 11 pulse accumulator . bits [3:0] ?not implemented always read zero pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16 tflg2 ?timer interrupt flag 2 $0025 bit 7 654321 bit 0 tof rtif paovf paif reset: 0000000 0
motorola mc68hc11ka4 58 mc68hc11ka4ts/d bit 7 ?not implemented always reads zero paen ?pulse accumulator system enable refer to 11 pulse accumulator . pamod ?pulse accumulator mode refer to 11 pulse accumulator . pedge ?pulse accumulator edge control refer to 11 pulse accumulator . bit 3 ?not implemented always reads zero i4/o5 ?input capture 4/output compare 5 configure ti4/o5 for input capture or output compare 0 = oc5 enabled 1 = ic4 enabled rtr[1:0] ?real-time interrupt (rti) rate refer to 10.1 real-time interrupt . 10.1 real-time interrupt the real-time interrupt (rti) function can generate interrupts at different fixed periodic rates. these rates are a function of the mcu oscillator frequency and the value of the software-accessible control bits, rtr1 and rtr0. these bits determine the rate at which interrupts are requested by the rti sys- tem. the rti system is driven by an e divided by 2 13 rate clock compensated so that it is independent of the timer prescaler. the rtr1 and rtr0 control bits select an additional division factor. rti is set to its fastest rate by default out of reset and can be changed at any time. refer to interrupt enable and flag bits in tmsk2 and tflg2 registers. pactl ?ulse accumulator control $0026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 0000000 0 table 11 real-time interrupt rates rtr [1:0] divide e by xtal = 8.0 mhz xtal = 12.0 mhz xtal = 16.0 mhz 0 0 2 13 4.096 ms 2.731 ms 2.048 ms 0 1 2 14 8.192 ms 5.461 ms 4.096 ms 1 0 2 15 16.384 ms 10.923 ms 8.192 ms 1 1 2 16 32.768 ms 21.845 ms 16.384 ms e = 2.0 mhz 3.0 mhz 4.0 mhz
mc68hc11ka4 motorola mc68hc11ka4ts/d 59 11 pulse accumulator the mc68hc11ka4/ka2 has an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. the counter can be read or written at any time. the port a bit 7 i/o pin can be configured to act as a clock in event counting mode, or as a gate signal to enable a free-running clock (e divided by 64) to the 8-bit counter in gated time accumulation mode. figure 18 pulse accumulator system block diagram selected common xtal frequencies crystal 8.0 mhz 12.0 mhz 16.0 mhz cpu clock (e) 2.0 mhz 3.0 mhz 4.0 mhz cycle time (1/e) 500 ns 333 ns 250 ns pulse accumulator (gated mode) (e/2 6) 1 count 32.0 m s 21.330 m s 16.0 m s (e/2 14 ) overflow 8.192 ms 5.461 ms 4.096 ms pedge pamod paen pactl control internal data bus pacnt 8-bit counter pa7/ pai/ oc1 interrupt requests paif paovf tflg2 interrupt status paovi paii paovf paovi paif paii tmsk2 int enables 1 2 overflow enable disable flag setting clock pai edge paen paen 2:1 mux output buffer input buffer and edge detector from main timer oc1 data bus pin e ? 64 clock (from main timer) from ddra7
motorola mc68hc11ka4 60 mc68hc11ka4ts/d toi ?timer overflow interrupt enable refer to 10 main timer . rtii ?real-time interrupt enable refer to 10 main timer . paovi ?pulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = pulse accumulator overflow interrupt enabled paii ?pulse accumulator input interrupt enable 0 = pulse accumulator input interrupt disabled 1 = pulse accumulator input interrupt enabled if paif bit in tflg2 register is set bits [3:2] ?not implemented always read zero pr[1:0] ?timer prescaler select refer to 10 main timer . note control bits [7:4] in tmsk2 correspond bit for bit with flag bits [7:4] in tflg2. ones in tmsk2 enable the corresponding interrupt sources. clear flags by writing a one to the corresponding bit position(s). tof ?timer overflow enable refer to 10 main timer . rtif ?real-time interrupt flag refer to 10 main timer . paovf ?pulse accumulator overflow flag set when pacnt changes from $ff to $00 paif ?pulse accumulator input edge flag set each time a selected active edge is detected on the pai input line bits [3:0] ?not implemented always read zero tmsk2 ?imer interrupt mask 2 $0024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 0000000 0 tflg2 ?imer interrupt flag 2 $0025 bit 7 654321 bit 0 tof rtif paovf paif reset: 0000000 0
mc68hc11ka4 motorola mc68hc11ka4ts/d 61 bit 7 ?not implemented always reads zero paen ?pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ?pulse accumulator mode 0 = event counter 1 = gated time accumulation pedge ?pulse accumulator edge control 0 = in event mode, falling edges increment counter. in gated accumulation mode, high level enables accumulator and falling edge sets paif. 1 = in event mode, rising edges increment counter. in gated accumulation mode, low level enables accumulator and rising edge sets paif. bit 3 ?not implemented always reads zero i4/o5 ?input capture 4/output compare 5 refer to 10 main timer . rtr[1:0] ?real-time interrupt rate refer to 10 main timer . can be read and written. pactl ?ulse accumulator control $0026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 0000000 0 pacnt ?ulse accumulator counter $0027 bit 7 654321 bit 0 bit 7 654321 bit 0
motorola mc68hc11ka4 62 mc68hc11ka4ts/d 12 pulse-width modulation timer the mc68hc11ka4/ka2 mcu contains a pwm timer that is composed of a four-channel 8-bit modu- lator. each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. the pwm provides up to four pulse-width modulated waveforms on specific port h pins. each channel has its own counter. pairs of counters can be concatenated to create 16-bit pwm outputs based on 16- bit counts. three clock sources (a, b, and s) give the pwm a wide range of frequencies. four control registers configure the pwm outputs ?pwclk, pwpol, pwscal, and pwen. the pw- clk register selects the prescale value for pwm clock sources and enables the 16-bit counters. the pwpol register determines each channel's polarity and selects the clock source for each channel. the pwscal register derives a user-scaled clock, based on the a clock source, and the pwen register enables the pwm channels. each channel has a separate 8-bit counter, period register, and duty cycle register. the period and duty cycle registers are double buffered so that if they are changed while the channel is enabled, the change does not take effect until the counter rolls over or the channel is disabled. with channels configured for 8-bit mode and e = 4 mhz, pwm signals of 40 khz (1% duty cycle reso- lution) to less than 10 hz (approximately 0.4% duty cycle resolution) can be produced. by configuring the channels for 16-bit mode with e = 4 mhz, pwm periods greater than one minute are possible. in 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a pwm frequen- cy of about 60 hz). in the same system, a pwm frequency of 1 khz corresponds to a duty cycle reso- lution of 0.025%.
mc68hc11ka4 motorola mc68hc11ka4ts/d 63 figure 19 pulse width modulation block diagram pwdty pwper pwm output ? 128 ? 1 ? 2 ? 4 ? 8 mcu e clock select pckb1 pckb2 pckb3 8-bit counter 8-bit compare = pwscal reset ? 2 clock a clock s pclk1 pclk2 pwen1 pwen2 con12 clock select bit 1 pwdty1 pwcnt1 pwcnt2 8-bit compare = pwdty2 pwper2 pwper1 16-bit pwm control con12 s r q carry reset bit 0 s r q mux ppol1 ppol2 ? 32 ? 64 cnt1 cnt2 q q mux ? 16 ph0/ pw1 8-bit compare = 8-bit compare = 8-bit compare = ph1/ pw2 port h pin control reset 8 8 8 bit 3 pwdty3 pwcnt3 pwcnt4 8-bit compare = pwdty4 pwper4 pwper3 16-bit pwm control con34 s r q carry reset bit 2 s r q mux ppol3 ppol4 q q mux ph2/ pw3 8-bit compare = 8-bit compare = 8-bit compare = ph3/ pw4 reset 8 8 pclk3 pclk4 pwen3 pwen4 con34 clock select cnt3 cnt4 select clock b pcka1 pcka2
motorola mc68hc11ka4 64 mc68hc11ka4ts/d con34 ?oncatenate channels 3 and 4 channel 3 is high-order byte, and channel 4 (port h, bit 3) is output. clock source is determined by pclk4. 0 = channels 3 and 4 are separate 8-bit pwms. 1 = channels 3 and 4 are concatenated to create one 16-bit pwm channel. con12 ?oncatenate channels one and two channel 1 is high order byte, and channel 2 (port h, bit 1) is output. clock source is determined by pclk2. 0 = channels 1 and 2 are separate 8-bit pwms 1 = channels 1 and 2 are concatenated to create one 16-bit pwm channel. pcka[2:1] ?rescaler for clock a (see also pwscal register) determines the rate of clock a bit 3 ?not implemented always reads zero pckb[3:1] ?prescaler for clock b determines the rate for clock b pwclk ?ulse-width modulation clock select $0060 bit 7 654321 bit 0 con34 con12 pcka2 pcka1 pckb3 pckb2 pckb1 reset: 00000000 pcka[2:1] value of clock a 0 0 e 0 1 e/2 1 0 e/4 1 1 e/8 pckb[3:1] value of clock b 0 0 0 e 0 0 1 e/2 0 1 0 e/4 0 1 1 e/8 1 0 0 e/16 1 0 1 e/32 1 1 0 e/64 1 1 1 e/128
mc68hc11ka4 motorola mc68hc11ka4ts/d 65 pclk4 ?pulse-width channel 4 clock select 0 = clock b is source 1 = clock s is source pclk3 ?pulse-width channel 3 clock select 0 = clock b is source 1 = clock s is source pclk2 ?pulse-width channel 2 clock select 0 = clock a is source 1 = clock s is source pclk1 ?pulse-width channel 1 clock select 0 = clock a is source 1 = clock s is source ppol[4:1] ?pulse-width channel x polarity 0 = pwm channel x output is low at the beginning of the clock cycle and goes high when duty count is reached 1 = pwm channel x output is high at the beginning of the clock cycle and goes low when duty count is reached scaled clock s is generated by dividing clock a by the value in pwscal, then dividing the result by 2. if pwscal = $00, divide clock a by 256, then divide the result by 2. tpwsl ?pwm scaled clock test bit (test) discp ?disable compare scaled e clock (test) bits [5:4] ?not implemented always read zero pwen[1:4] ?pulse-width channel 1? 0 = channel disabled 1 = channel enabled pwpol ?ulse-width modulation timer polarity $0061 bit 7 654321 bit 0 pclk4 pclk3 pclk2 pclk1 ppol4 ppol3 ppol2 ppol1 reset: 0000000 0 pwscal ?pulse-width modulation timer prescaler $0062 bit 7 654321 bit 0 7654321 0 reset: 0000000 0 pwen ?pulse-width modulation timer enable $0063 bit 7 654321 bit 0 tpwsl discp pwen4 pwen3 pwen2 pwen1 reset: 0000000 0
motorola mc68hc11ka4 66 mc68hc11ka4ts/d pwcnt[1:4] begins count using whichever clock was selected pwper[1:4] determines period of associated pwm channel pwdty[1:4] determines duty cycle of associated pwm channel pwcnt[1:4] ?pulse-width modulation timer counter 1 to 4 $0064?0067 $0064 bit 7 654321 bit 0 pwcnt1 $0065 bit 7 654321 bit 0 pwcnt2 $0066 bit 7 654321 bit 0 pwcnt3 $0067 bit 7 654321 bit 0 pwcnt4 reset: 00000000 pwper[1:4] ?ulse-width modulation timer period 1 to 4 $0068?006b $0068 bit 7 654321 bit 0 pwper1 $0069 bit 7 654321 bit 0 pwper2 $006a bit 7 654321 bit 0 pwper3 $006b bit 7 654321 bit 0 pwper4 reset: 11111111 pwdty[1:4] ?pulse-width modulation timer duty cycle 1 to 4 $006c?006f bit 7 654321 bit 0 $006c bit 7 654321 bit 0 pwdty1 $006d bit 7 654321 bit 0 pwdty2 $006e bit 7 654321 bit 0 pwdty3 $006f bit 7 654321 bit 0 pwdty4 reset: 11111111
mc68hc11ka4 motorola mc68hc11ka4ts/d 67
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